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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11410-2E
MEMORY
CMOS
2 x 512K x 32-BIT SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB811L323229-12/18
s DESCRIPTION
The Fujitsu MB811L323229 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*) containing 33,554,432 memory cells accessible in a 32-bit format. The MB811L323229 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB811L323229 is utilized using Fujitsu advanced FCRAM core technology and designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM). The MB811L323229 is dedicated for SiP (System in a package), and ideally suited for various embedded/ consumer applications including digital AVs and image processing where a large band width and low power consumption memory is needed. *: FCRAM is a trademark of Fujitsu Limited, Japan.
s PRODUCT LINE
Parameter Clock Frequency CL - tRCD - tRP CL = 2 Burst Mode Cycle Time CL = 2 Access Time from Clock CL = 2 Operating Current Power Down Mode Current (ICC2PS) Self Refresh Current (ICC6) MB811L323229-12 81 MHz Max 2 - 2 - 2 clk Min 12 ns Min 9 ns Max 120mA Max 1 mA Max 2.5 mA Max MB811L323229-18 54 MHz Max 2 - 2 - 2 clk Min 18 ns Min 9 ns Max 80mA Max 1 mA Max 2.5 mA Max
MB811L323229-12/18
s FEATURES
* * * * * * * VCCQ: +3.3V Supply 0.3V tolerance or +2.5V Supply 0.2V tolerance VDD: +2.5 V Supply 0.2 V tolerance LVCMOS compatible I/O interface 2 K refresh cycles every 32 ms Two bank operation (512 K word x 32 bit x 2 bank) Burst read/write operation and burst read/single write operation capability Programmable burst type and burst length Burst type : Sequential Mode, Interleave Mode Burst length : BL = 1, 2, 4, 8, full column (256) CAS latency = 2 Auto-and Self-refresh CKE power down mode Byte control with DQM0 to DQM3
* * * *
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s PAD LAYOUT
BME VSS VDD DQ24 DQ23 VSSQ VCCQ DQ25 DQ22 DQ26 DQ21 DQ27 DQ20 DQ28 DQ19 DQ29 DQ18 DQ30 DQ17 VCCQ VSSQ DQ31 DQ16 VSSI VSS VDDI VDD DQM3 DQM2 DSE A3 A2 A4 A1 A5 A0 A6 A10/AP A7 VSS VDD A8 BA A9 CKE CSB CLK RASB CASB WEB DQM1 DQM0 VSSI VSS VDDI VDD DQ8 DQ7 VCCQ VSSQ DQ9 DQ6 DQ10 DQ5 DQ11 DQ4 DQ12 DQ3 DQ13 DQ2 DQ14 DQ1 VSSQ VCCQ DQ15 DQ0 VSS VDD
PADNo.88
PAD
PADNo.1
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s PAD DESCRIPTIONS
Symbol VCCQ, VDD, VDDI DQ0 to DQ31 VSS, VSSQ, VSSI -- WE(WEB) CAS(CASB) RAS(RASB) CS(CSB) BA AP A0 to A10 CKE CLK DQM0 to DQM3 DSE BME Supply Voltage Data I/O Ground Don't Bond Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select (Bank Address) Auto Precharge Enable Address Input Clock Enable Clock Input Data Input /Output Mask Disable (apply VSS except DISABLE mode) Burn in Mode Entry (apply VSS except Burn in mode) Row: A0 to A10 Column: A0 to A7 Function
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s BLOCK DIAGRAM
MB811L323229 BLOCK DIAGRAM
CLK
To each block CLOCK BUFFER
CKE
BANK-1 BANK-0
RAS
CS RAS CAS WE DSE BME
CONTROL SIGNAL LATCH COMMAND DECODER
CAS
WE
FCRAM CORE (2,048 x 256 x 32) MODE REGISTER
A0 ~ A9, A10/AP BA
ROW ADDR. ADDRESS BUFFER/ REGISTER COLUMN ADDRESS COUNTER
COL. ADDR.
I/O
DQM0 ~ DQM3
DQ0 ~ DQ31
I/O DATA BUFFER/ REGISTER
VCCQ VDD VDDI VSS VSSQ VSSI
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s FUNCTIONAL TRUTH TABLE
1. Command Truth Table
Function Device Deselect *1 No Operation * Burst Stop *2 Read *3 Read with Auto-precharge *3 Write *3 Write with Auto-precharge *3 Bank Active *4 Precharge Single Bank Precharge All Banks Mode Register Set *5, *6
1
Command DESL NOP BST READ READA WRIT WRITA ACTV PRE PALL MRS
CKE CS n-1 H H H H H H H H H H H n X X X X X X X X X X X H L L L L L L L L L L X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L X X X V V V V V V X X RAS CAS WE BA
A10 (AP) X X X L H L H V L H X
A9 to A8 X X X X X X X V X X V
A7 to A0 X X X V V V V V X X V
V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. *1 : NOP and DESL commands have the same effect on the part. The both commands have the device hold the internal operation. *2 : BST command is effective for all burst length (BL = 1, 2, 4, 8, full column (256) ) . *3 : READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to "s STATE DIAGRAM (Simplified for Single Bank Operation State Diagram)." *4 : ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL command). *5 : Required after power up. Refer to "18. Power-Up Initialization" in "s FUNCTIONAL DESCRIPTION." *6 : MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer to "s STATE DIAGRAM (Simplified for Single Bank Operation State Diagram) ." Notes : * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of clock.
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2. DQM Truth Table
Function Data Input/Output Enable Data Input/Output Disable Command ENBi *1 MASKi *
1
CKE n-1 H H n X X
DQMi *1,*2 L H
V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. *1 : i = 0, 1, 2, 3 *2 : DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31 Notes : * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock.
3. CKE Truth Table
Current State Bank Active Any Clock Suspend Idle Idle Self Refresh Idle Function Clock Suspend Mode Entry *1 Clock Suspend Continue *1 Clock Suspend Mode Exit Auto-refresh Command *2 Self-refresh Entry * * Self-refresh Exit *4 Power Down Entry *3
2, 3
Command CSUS REF SELF SELFX PD
CKE n-1 H L L H H L L H H L L n L L H H L H H L L H H CS RAS CAS WE X X X L L L H L H L H X X X L L H X H X H X X X X L L H X H X H X X X X H H H X H X H X BA X X X X X X X X X X X
A10 (AP) X X X X X X X X X X X
A9 to A0 X X X X X X X X X X X
Power Down Power Down Exit
V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. *1 : The CSUS command requires that at least one bank is active. Refer to "s STATE DIAGRAM (Simplified for Single Bank Operation State Diagram." NOP or DSEL commands should only be issued after CSUS and PRE (or PALL) commands asserted at the same time. *2 : REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL command). Refer to "s STATE DIAGRAM (Simplified for Single Bank Operation State Diagram) ." *3 : SELF and PD commands should only be issued after the last read data have been appeared on DQ. *4 : CKE should be held high within one tRC period after tCKSP . Notes : * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock. 7
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4. Operation Command Table (Applicable to single bank)
Current State CS H L L L Idle L L L L L H L L L Bank Active L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS NOP NOP NOP Illegal *1 Illegal *1 Bank Active after tRCD NOP Auto-refresh or Self-refresh *2, *5 Mode Register Set (Idle after tRSC) *2, *6 NOP NOP NOP Start Read; Determine AP Start Write; Determine AP Illegal *1 Start Precharge; Determine Precharge Type Illegal Illegal Function
(Continued)
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Current State
CS H L L L
RAS CAS WE X H H H X H H L X H L H
Addr X X X BA, CA, AP
Command DESL NOP BST READ/READA
Function Continue Burst to End Bank Active Continue Burst to End Bank Active Burst Stop Bank Active Terminate Burst, New Read; Determine AP Terminate Burst, Start Write; Determine AP *3 Illegal *1 Terminate Burst, Start Precharge Idle; Determine Precharge Type Illegal Illegal Continue Burst to End Write Recovery Continue Burst to End Write Recovery Burst Stop Bank Active Terminate Burst, Start Read; Determine AP *3 Terminate Burst, New Write; Determine AP Illegal *1 Terminate Burst, Start Precharge; Determine Precharge Type Illegal Illegal
Read
L L L L L H
H L L L L X
L H H L L X
L H L H L X
BA, CA, AP BA, RA BA, AP X MODE X
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL
L L L Write L L L L L
H H H
H H L
H L H
X X BA, CA, AP
NOP BST READ/READA
H L L L L
L H H L L
L H L H L
BA, CA, AP BA, RA BA, AP X MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS
(Continued)
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Current State
CS
RAS CAS WE
Addr
Command
Function Continue Burst to End Precharge Idle Continue Burst to End Precharge Idle Illegal Illegal *1 Illegal *1 Illegal *1 Illegal *1 Illegal Illegal Continue Burst to End Precharge Idle Continue Burst to End Precharge Idle Illegal Illegal *1 Illegal *1 Illegal *1 Illegal *1 Illegal Illegal
H
X
X
X
X
DESL
L L Read with Autoprecharge L L L L L L H
H H H H L L L L X
H H L L H H L L X
H L H L H L H L X
X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X
NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL
L L Write with Autoprecharge L L L L L L
H H H H L L L L
H H L L H H L L
H L H L H L H L
X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE
NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS
(Continued)
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Current State
CS H L L L
RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L
Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS Idle after tRP Idle after tRP Idle after tRP Illegal *1 Illegal *1 Illegal *1
Function
Precharging
L L L L L H L L L
PALL may affect other bank *4 Illegal Illegal Bank Active after tRCD Bank Active after tRCD Bank Active after tRCD Illegal *1 Illegal *1 Illegal *1 Illegal *1 Illegal Illegal
Bank Activating
L L L L L
(Continued)
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(Continued)
Current State CS H L L Refreshing L L H L Mode Register Setting L L L L X H H H H L X H H L X X X H L X X X X X X X RAS X H H CAS X H L WE X X X Addr X X X Command DESL NOP/BST Idle after tRC Idle after tRC Function
READ/READA/ Illegal WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS DESL NOP BST Illegal Illegal Idle after tRSC Idle after tRSC Illegal
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS Illegal
L
L
X
X
X
ABBREVIATIONS: L = Logic Low, H = Logic High, X = either L or H RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge *1 : Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *2 : Illegal if any bank is not idle. *3 : Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4) and 12. WRITE to READ Timing (Example @CL = 2, BL = 4) " in "s TIMING DIAGRAMS." *4 : NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP). *5 : SELF command should only be issued after the last read data have been appeared on DQ. *6 : MRS command should only be issued on condition that all DQ are in High-Z. Notes : * All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don't used command. If used, power up sequence be asserted after power shout down. * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock. * All entries in "4. Operation Command Table" assume that the CKE was High during the proceeding clock cycle and the current clock cycle. * Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down. 12
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5. Command Truth Table for CKE
Current State CKE n-1 H L Selfrefresh L L L L L L H H Selfrefresh Recovery H H H H H H L Power Down L L L L n X H H H H H L X H H H H H H L X H H L H H CS X H L L L L X X H L L L L X X X H L X L L RAS X X H H H L X X X H H H L X X X X H X L H CAS X X H H L X X X X H H L X X X X X H X X L WE X X H L X X X X X H L X X X X X X H X X X Addr X X X X X X X X X X X X X X X X X X X X X Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Exit Self-refresh (Self-refresh Recovery Idle after tRC) Illegal Illegal Illegal Maintain Self-refresh Invalid Idle after tRC Idle after tRC Illegal Illegal Illegal Illegal Illegal * Invalid Exit Power Down Mode Idle Maintain Power Down Mode Illegal Illegal Function
(Continued)
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(Continued)
Current State Bank Active, Bank Activating, Read/Write, All Banks idle , Refreshing, Precharging Clock Suspend Any State Other Than Listed Above CKE n-1 H H L H L L L H H n H L X X H L X H L CS X X X X X X X X X RAS X X X X X X X X X CAS X X X X X X X X X WE X X X X X X X X X Addr X X X X X X X X X Function Refer to "Operation Command Table". Refer to "Operation Command Table". Start Clock Suspend next cycle Invalid Invalid Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer to "Operation Command Table". Illegal
V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n-1 = state at 1 clock cycle before n. * : CKE should be held High for tRC period after tCKSP . Notes : * All entries in "5. Command Truth Table for CKE" are specified at CKE(n) state and CKE input from CKE(n-1) to CKE(n) state must satisfy corresponding set up and hold time for CKE. * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock.
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s FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM Basic Function
Three major differences between this SDR I/F FCRAMs and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for the synchronization, while the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDR I/F FCRAM is determined by commands and all operations are referenced to a positive clock edge. "BASIC TIMING FOR CONVENTIONAL DRAM VS SDR I/F CRAM" shows the basic timing diagram differences between SDR I/F FCRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDR I/F FCRAM operation and function into desired system conditions. "s MODE REGISTER TABLE" shows how SDR I/F FCRAM can be configured for system requirement by mode register programming. The program to the mode register should be executed after all banks are precharged.
2. FCRAMTM
MB811L323229 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. Clock Input (CLK) and Clock Enable (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the a rising edge of CLK. CKE is a high active clock enable signal. CKE controls the internal clock generator. CKE is latched by a rising edge of CLK. CKE should become High level on the previous clock cycle when a basic command is issued. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current.
4. Chip Select (CS)
CS enables all commands inputs, RAS, CAS, WE, and address input. When CS is High, command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, CS can be tied to ground level.
5. Command Input (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDR I/F FCRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge of the CLK determines SDR I/F FCRAM operation. Refer to "s FUNCTIONAL TRUTH TABLE."
6. Address Input (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen address input signals are required to decode such a matrix. SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially latched and the remainder of eight Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA).
7. Bank Select (BA)
This SDR I/F FCRAM has two banks and each bank is organized as 512 K words by 32-bit. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and precharge command (PRE). 15
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8. Data Input and Output (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input: tRAC ; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.) tCAC ; from the read command when tRCD is greater than tRCD (Min). (This parameter is reference only.) tAC ; from the previous clock edge when output data is valid. The polarity of the output data is identical to that of the input data. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH). Refer to "s AC CHARACTERISTICS."
9. Data I/O Mask (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. DQM0, DQM1, DQM2 and DQM3 control DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31, respectively.
10. Burst Mode Operation and Burst Type
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read 1st Step Burst Write 2nd Step Burst Write Burst Read Precharge Precharge Write Command after Write Command Read Command Precharge Command Precharge Command
OWD
Method (Assert the following command) Read Command Mask Command (Normally 3 clock cycles)
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the next address will be odd (1), or vice-versa.
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Burst Length 2
Starting Column Address A2 X X X X X X 0 0 0 0 1 1 1 1 A1 X X 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave Mode 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
11. Full Column Burst and Burst Stop Command (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps around to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT), precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When read mode is interrupted by BST command, the output will be in High-Z. For the detail rule, please refer to "8. READ Interrupted by Burst Stop (Example @ CL = 2, BL = Full Column) " in "s TIMING DIAGRAMS." When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored.
12. Burst READ & Single WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not be affected by this mode.
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13. Precharge and Precharge Option (PRE, PALL)
SDR I/F FCRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDR I/F FCRAM will automatically be in standby state after precharge time (tRP). The precharged bank is selected by combination of AP and BA when Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (PALL). If AP = Low, a bank to be selected by BA is precharged (PRE). The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "s FUNCTIONAL TRUTH TABLE."
14. Auto-Refresh (REF)
Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 15.6 s or a total 2048 refresh commands within 32 ms period.
15. Self-Refresh Entry (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 2 ms prior to the self-refresh mode entry.
16. Self-Refresh Exit (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one tRC period after tCKSP Refer to "16. Self-Refresh Entry and Exit Timing" in "s TIMING DIAGRAMS" for . the detail. It is recommended to assert an Auto-refresh command just after tRC period to avoid the violation of refresh period. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 2 ms after the self-refresh exit.
17. Mode Register Set (MRS)
The mode register of SDR I/F FCRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to "s MODE REGISTER TABLE." The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDR I/F FCRAM. Refer to "18. Power-Up Initialization".
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MB811L323229-12/18
18. Power-Up Initialization
SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply power (VDD and VDDI should be applied before or in parallel with VCCQ)and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. 3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). 4. Assert minimum of 2 Auto-refresh command (REF). 5. Program the mode register by Mode Register Set command (MRS). In addition, it is recommended DQM and CKE to track VDD to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh command (REF). It is possible to execute 5, after 4.
19. Disable
When DSE PAD is applied high level, SDR I/F FCRAM entries DISABLE mode. This command entry doesn't require clock. In DISABLE mode, SDR I/F FCRAM current consumption is less than ICC2PS and output is HighZ. Any command isn't accepted in this mode. To exit DISABLE mode, apply Low level to DSE PAD.
20. Burn IN
When BME PAD is applied High level, SDR I/F FCRAM entries BURN IN mode. In BURN IN mode, self refresh function is asserted internally. This command doesn't require clock. Any command isn't accepted in this mode. To exit BURN IN mode, apply Low level to BME PAD.
19
MB811L323229-12/18
BASIC TIMING FOR CONVENTIONAL DRAM VS SDR I/F FCRAM
CLK
Active Read/Write Precharge
H
H
H
CKE
tSI
tHI
CS
RAS
CAS
H : Read
WE
L : Write
Address
BA RA BA CA CAS Latency = 2 BA AP (A10)
DQ0 to DQ31
Burst Length = 4

Row Address Select Columm Address Select Precharge
RAS
CAS
DQ0 to DQ31
20
MB811L323229-12/18
s STATE DIAGRAM (Simplified for Single Bank Operation State Diagram)
MODE REGISTER SET
MRS
SELF
IDLE
SELFX
SELF REFRESH
REF CKE\ (PD) ACTV CKE
AUTO REFRESH
POWER DOWN
BANK ACTIVE SUSPEND
CKE\ (CSUS) CKE BST
BANK ACTIVE
BST
WRIT
WRIT WRITA READA READ
READ
READ
WRITE SUSPEND
CKE
CKE
WRITE
WRIT CKE\ (CSUS) WRITA CKE READA WRITA
READ
READ SUSPEND
CKE\ (CSUS) READA
PRE or PALL
WRITE SUSPEND
WRITE WITH AUTO PRECHARGE
PRE or PALL
READ WITH AUTO PRECHARGE
PRE or PALL
CKE
READ SUSPEND
CKE\ (CSUS)
CKE\ (CSUS)
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED
DEFINITION OF ALLOWS
Manual Input Automatic Sequence
Note : CKE\ means CKE goes Low-level from High-level.
21
MB811L323229-12/18
s BANK OPERATION COMMAND TABLE
* Minimum Clock Latency or Delay Time for 1 Bank Operation READA ACTV
Second command (same bank)
*4 *4
WRITA
READ
SELF
MRS
PALL
PRE
REF
First command
MRS
tRSC
tRSC
WRIT
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD *5 1
tRCD *5 1
tRAS *4 1 *4 BL + tRP
tRAS *4 1 *4 BL + tRP *4 tDPL *4 BL-1 + tDAL *4 1 *2 BL-1 + tDAL *2 tRP *2 BL-1 + tDAL *2, *6 tRP *6 tRP *2 BL + tRP *2, *7 BL + tRP
READ *1, *2 BL + tRP
1
1
READA
BL + tRP tWR tWR 1 1
WRIT *2 BL-1 + tDAL *2, *3 tRP *3 tRP
*4 tDPL *4 BL-1 + tDAL 1
WRITA
BL-1 + tDAL tRP
PRE
PALL
tRP
1
1
tRP
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
tRC
tRC
tRC
tRC
*1 : If tRP(Min) CLxtCK, minimum latency is a sum of (BL+CL)xtCK. *2 : Assume all banks are in Idle state. *3 : Assume output is in High-Z state. *4 : Assume tRAS(Min) is satisfied. *5 : Assume no I/O conflict. *6 : Assume after the last data have been appeared on DQ. *7 : If tRP(Min) (CL-1)xtCK, minimum latency is a sum of (BL+CL-1)xtCK. Illegal Command 22
BST 1 1 1 1 1
MB811L323229-12/18
* Minimum Clock Latency or Delay Time for Multi Bank Operation READA WRITA ACTV SELF MRS PALL
Second command (same bank)
*5 *5, *6 *5 *5, *6
READ
WRIT
PRE
REF
First command
MRS
tRSC
tRSC *2 tRRD *2, *4 1 *7 1 *7 1 *7 1 *10 1 *6, *10 1 *7 1 *10 1 *6, *10 1
tRSC *6, *7 1 *6 1 *6 1 *6 1 *6 1 *6, *7 1
tRSC *7 tRAS *6 1 *6 BL+ tRP *6 tDPL *6 BL-1 + tDAL *7 1
tRSC
tRSC
tRSC
ACTV
READ *1, *2 BL+ tRP
1 *6 1
1 *6 1
READA
*2, *4 1 *2, *4 1
*2 BL+ tRP
*2, *9 BL+ tRP 1
WRIT *2 BL-1 + tDAL *2, *3 tRP *3 tRP
1 *6 1 *7 1
1 *6 1 *7 1
1 *6 1 *7 1
1 *6 1 *7 1
*2, *4 1 *2, *4 1
WRITA
*2 BL-1 + tDAL *2 tRP
*2 BL-1 + tDAL *2, *8 tRP *8 tRP 1
PRE
PALL
tRP
1
1
tRP
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX *1 *2 *3 *4 *5 *6 *7 *8 *9 *10
tRC
tRC
tRC
tRC
tRC
tRC
tRC
: If tRP(Min) CLxtCK, minimum latency is a sum of (BL+CL)xtCK. : Assume bank of the object is in Idle sate. : Assume output is in High-Z sate. : tRRD(Min) of other bank (second command will be asserted) is satisfied. : Assume other bank is in active, read or write state. : Assume tRAS(Min) is satisfied. : Assume other banks are not in READA/WRITA state. : Assume after the last data have been appeared on DQ. : If tRP(Min) (CL-1)xtCK, minimum latency is a sum of (BL+CL-1)xtCK. : Assume no I/O conflict. Illegal Command
BST 1 1 1 23
MB811L323229-12/18
s MODE REGISTER TABLE
MODE REGISTER SET BA A10 A9
Opcode
A8 0
*3
A7 0
*3
A6
A5 CL
A4
A3 BT
A2
A1 BL
A0
ADDRESS
MODE REGISTER
0 or 1
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length BT = 0 1 2 4 8 Reserved Reserved Reserved Full Column BT = 1 *2 Reserved 2 4 8 Reserved Reserved Reserved Reserved
Reserved Reserved 2 Reserved Reserved Reserved Reserved Reserved
A9 0 1
Op-code Burst Read & Burst Write *1 Burst Read & Single Write
A3 0 1
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up)
*1 : When A9 = 1, burst length at Write is always one regardless of BL value. *2 : BL = 1 and Full Column are not applicable to the interleave mode. *3 : A7 = 1 and A8 = 1 are reserved for vender test.
24
MB811L323229-12/18
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage of VCCQ Supply Relative to VSS Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VCCQ VDD, VDDI VIN, VOUT IOUT PD TSTG Rating Min -0.5 -0.5 -0.5 -50 -- -55 Max +4.6 +3.6 +4.6 +50 1.0 +125 Unit V V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS) Parameter VCCQ Supply Voltage Symbol 3.3V I/O 2.5V I/O Value Min 3.0 2.3 2.3 0 2.4 2.0 -0.5 0 Typ 3.3 2.5 2.5 0 -- -- -- -- Max 3.6 2.7 2.7 0 VCCQ + 0.5 VCCQ + 0.5 0.4 70 Unit V V V V V V V C
VDD, VDDI VSS, VSSQ, VSSI 3.3V I/O 2.5V I/O VIL TA
Input High Voltage *1 Input Low Voltage *2 Ambient Temperature
VIH
*1 : Overshoot limit: VIH (Max) = 4.6V for pulse width 5 ns acceptable, pulse width measured at 50% of pulse ampli4.6 V
*2 : Undershoot limit: VIL (Min) = VSS -1.5V for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude. Pulse width 5 ns VIH
VIL (Max) VIL -1.5 V
VIH VIH (Min) VIL
50% of pulse amplitude Pulse width 5 ns
50% of pulse amplitude
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25
MB811L323229-12/18
s CAPACITANCE
(TA = +25C, f = 1 MHz) Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance (DQ0 to DQ31) Symbol CIN1 CIN2 CI/O Value Min 1.5 1.5 2.0 Typ -- -- -- Max 5.0 4.0 6.0 Unit pF pF pF
26
MB811L323229-12/18
s DC CHARACTERISTICS
Parameter (At recommended operating conditions unless otherwise noted.) Value Symbol Condition Unit Min Max 3.3V I/O IOH = -2 mA Output High Voltage VOH(DC) 2.5V I/O IOH = -0.5 mA 3.3V I/O IOL = 2 mA Output Low Voltage VOL(DC) 2.5V I/O IOL = 0.5 mA Input Leakage Current (Any Input except for DSE,BME) Input Leakage Current (DSE,BME) Input Pull Down Resistance (DSE, BME) ILI 0 V VIN VCCQ; All other pins not under test = 0 V VIN = 0 V All other pins not under test = 0V -- -5 0.4 +5 V A 2.0 -- -- 0.4 V V 2.4 -- V
ILIPD
-5
+5
A
RPD
5
20
k
Output Leakage Current
ILO
0 V VIN VCCQ; High impedance Burst Length = 1, tCK = Min, tRC = Min, One bank active, Output pin open, Adrress changed up to 1 - time during tRC (Min), 0 V VIN VIL Max, VIH Min VIN VCCQ
-5
+5
A
MB811L323229-12 Operating Current (Average Power Supply Current) MB811L323229-18 ICC1
120 -- 80 mA
(Continued)
27
MB811L323229-12/18
Parameter
Symbol
Condition CKE = VIL, All banks idle, tCK = Min, Power down mode, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIL, All banks idle, CLK = VIH or VIL, Power down mode, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIH, All banks idle, tCK = Min, NOP commands only, Input signals (except to CMD) are changed 1 time during 2 clocks, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIH, All banks idle, CLK = VIH or VIL, Input signal are stable, 0 V VIN VIL Max, VIH Min VIN VCCQ
Value Min Max
Unit
ICC2P
--
2
mA
ICC2PS Power Supply Current (Precharge Standby Current)
--
1
mA
MB811L323229-12 ICC2N MB811L323229-18
12 -- 8 mA
ICC2NS
--
2
mA
(Continued)
28
MB811L323229-12/18
(Continued)
Parameter Symbol Condition CKE = VIL, Any bank active, tCK = Min, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIL, Any bank active, CLK = VIH or VIL, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIH, Any bank active, tCK = Min, NOP commands only, Input signals (except to CMD) are changed 1 time during 2 clocks, 0 V VIN VIL Max, VIH Min VIN VCCQ CKE = VIH, Any bank active, CLK = VIH or VIL, Input signals are stable, 0 V VIN VIL Max, VIH Min VIN VCCQ tCK = Min, Burst Length = 4, Output pin open, All-banks active, Gapless data output, 0 V VIN VIL Max, VIH Min VIN VCCQ Auto-refresh; tCK = Min, tRC = Min, 0 V VIN VIL Max, VIH Min VIN VCCQ Self-refresh; tCK = Min, CKE 0.2 V, 0 V VIN VIL Max, VIH Min VIN VCCQ Value Min Max Unit
ICC3P
--
2
mA
ICC3PS
--
1
mA
Power Supply Current (Active Standby Current)
MB811L323229-12 ICC3N MB811L323229-18
37.5 -- 25 mA
ICC3NS
--
2
mA
Average Power Supply Current (Burst mode Current)
MB811L323229-12 ICC4 MB811L323229-18
143 -- 95 mA
Average Power Supply Current (Refresh Current #1)
MB811L323229-12 ICC5 MB811L323229-18
150 -- 100 mA
Average Power Supply Current (Refresh Current #2)
ICC6
--
2.5
mA
Notes : * All voltages are referenced to VSS. * DC characteristics are measured after following the 18. Power-Up Initialization procedure in "s FUNCTIONAL DESCRIPTION." * ICC depends on the output termination or load condition, clock cycle rate, signal clocking rate. The specified values are obtained with the output open and no termination register.
29
MB811L323229-12/18
s AC CHARACTERISTICS
(1) AC Characteristics (At recommended operating conditions unless otherwise noted.) MB811L323229-12 MB811L323229-18 Parameter Clock Period Clock High Time Clock Low Time Input Setup Time Input Hold Time Access Time from Clock (tCK =Min) *2,*3,*4 Output in Low-Z *2 Output in High-Z *2,*5 Output Hold Time *2,*4 Time between Auto-Refresh command interval *1 Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time *2 *1 : This value is for reference only. *2 : If input signal transition time (tT) is longer than 1 ns; [(tT/2) - 0.5] ns should be added to tAC (Max), tHZ (Max), and tCKSP (Min) spec values, [(tT/2) - 0.5] ns should be subtracted from tLZ (Min), tHZ (Min), and tOH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min), tCL (Min), tSI (Min), and tHI (Min) spec values. *3 : tAC also specifies the access time at burst mode. *4 : tAC and tOH are measured under OUTPUT LOAD CIRCUIT shown in "OUTPUT LOAD CIRCUIT". *5 : Specified where output buffer is no longer driven. Notes : * AC characteristics are measured after following the POWER-UP INITIALIZATION procedure. (See "18. Power-Up Initialization in s FUNCTIONAL DESCRIPTION.) * AC characteristics assume tT = 1 ns, 10 pF of capacitive load and 50 of terminated load. * 1.4 V is the reference level for 3.3 V I/O for measuring timing of input signals. 1.2 V is the reference level for 2.5 V I/O for measuring timing of input signals. Transition times are measured between VIH (Min) and VIL (Max). CL = 2 CL = 2 CL = 2 CL = 2 Symbol Min tCK2 tCH tCL tSI tHI tAC2 tLZ tHZ2 tOH tREFI tREF tT tCKSP 12 tCK x 0.3 tCK x 0.3 3 1.5 -- 0 2 2 -- -- 0.5 3 Max -- -- -- -- -- 9 -- 9 -- 15.6 32 10 -- Min 18 tCK x 0.4 tCK x 0.4 4 1.5 -- 0 2 2 -- -- 0.5 4 Max -- -- -- -- -- 9 -- 9 -- 15.6 32 10 -- ns ns ns ns ns ns ns ns ns s ms ns ns Unit
30
MB811L323229-12/18
(2) Base Values for Clock Count/Latency MB811L323229-12 Parameter RAS Cycle Time * RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Data-in to Precharge Lead Time Data-in to Active/Refresh Command Period Mode Resister Set Cycle Time * : Actual clock count of tRC (
RC)
MB811L323229-18 Unit Min 108 36 72 36 18 36 18 1 cyc + tRP 36
RP).
Symbol Min tRC tRP tRAS tRCD tWR tRRD tDPL CL=2 tDAL2 tRSC 72 24 48 24 18 24 12 1 cyc + tRP 24
RAS)
Max -- -- 110000 -- -- -- -- -- -- and tRP (
Max -- -- 110000 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns
will be sum of clock count of tRAS (
(3) CLOCK COUNT FORMULA Clock cycle Base Value Clock Period (Round up a whole number)
Note : All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number).
31
MB811L323229-12/18
(4) LATENCY - FIXED VALUES (The latency values on these parameters are fixed regardless of clock period.) Parameter CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (Min) CAS Bank Delay (Min) Symbol MB811L323229-12 MB811L323229-18
CKE DQZ DQD OWD DWD ROH2 BSH2 CCD CBD
Unit cycle cycle cycle cycle cycle cycle cycle cycle cycle
1 2 0 2 0 2 2 1 1
1 2 0 2 0 2 2 1 1
OUTPUT LOAD CIRCUIT
R1 = 50
Output
1.4 V (3.3 V I/O) 1.2 V (2.5 V I/O) CL = 10 pF
Note : By adding appropriate correlation factors to the test conditions, tAC and tOH measured when the Output is coupled to the Output Load Circuit are within specifications.
32
MB811L323229-12/18
(5) Timing Diagram, Setup, Hold and Delay Time
tCK2 tCH tCL 2.4 V (3.3 V I/O) 2.0 V (2.5 V I/O) 0.4 V
CLK
1.4 V (3.3 V I/O) 1.2 V (2.5 V I/O) tSI tHI
Input (Control, Addr. & Data)
VALID
tAC2 tLZ
2.4 V (3.3 V I/O) 1.4 V (3.3 V I/O) 2.0 V (2.5 V I/O) 1.2 V (2.5 V I/O) 0.4 V tHZ2 tOH
Output
2.4 V (3.3 V I/O) 2.0 V (2.5 V I/O) 0.4 V
1.4 V (3.3 V I/O) 1.2 V (2.5 V I/O)
VALID
Notes : * Reference level of input signal is 1.4 V for LVCMOS (3.3V I/O),1.2V for LVCMOS (2.5V I/O). * Access time is measured at 1.4 V for LVCMOS (3.3V I/O),1.2V for LVCMOS (2.5V I/O). * AC characteristics are also measured in this condition.
(6) Timing Diagram, Delay Time for Power Down Exit
CLK
H or L tCKSP (Min) 1 clock (Min)
CKE
Command
H or L
NOP
NOP
ACTV
33
MB811L323229-12/18
(7) Timing Diagram, Pulse Width
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
Input (Control)
tDPL, tDAL, tRSC, tRRD, tCKSP COMMAND COMMAND
Invalid Data
Notes : * These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the latency value from the rising edge of CKE. * Measurement reference voltage is 1.4 V (3.3V I/O) or 1.2V (2.5V I/O).
(8) Timing Diagram, Access Time
CLK
Command
READ
tAC2 (CAS Latency-1) x tCK
tAC2
tAC2
DQ (Output)
Q (Valid)
Q (Valid)
Q (Valid)
34
MB811L323229-12/18
s TIMING DIAGRAMS
1. Clock Enable - READ and WRITE Suspend (@ BL = 4)
CSUS Command CSUS Command
CLK
CKE
CKE *1 CKE *1
(1 clock)
(1 clock)
*2 *2
CLE (Internal)
DQ (Read)
Q1
Q2 (NO CHANGE)
*2
Q3 (NO CHANGE)
*2
Q4
DQ (Write)
D1
NOT *3 WRITTEN
D2
NOT *3 WRITTEN
D3
D4
*1 : The latency of CKE (
CKE)
is one clock.
*2 : During read mode, burst counter will not be increased or decreased at the next clock of CSUS command. Output data remain the same data.0 *3 : During the write mode, data at the next clock of CSUS command is ignored.
2. Clock Enable - Power Down Entry and Exit
CLK
tCKSP (Min) 1 clock (Min)
CKE
Command
NOP
*1
PD (NOP)
*2
H or L tREF (Max)
NOP
*3
NOP
*3
ACTV
*4
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2 : Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ. *3 : It is recommended to apply NOP command in conjunction with CKE. *4 : The ACTV command can be latched after tCKSP (Min) + 1 clock (Min).
35
MB811L323229-12/18
3. Column Address to Column Address Input Delay
CLK
RAS
CCD
tRCD (Min)
(1 clock)
CCD
CCD
CCD
CAS
Address
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
Note : CAS to CAS delay can be one or more clock period.
4. Different Bank Address Input Delay
CLK
tRRD (Min)
RAS
CBD
tRCD (Min) or more
(1 clock)
CBD
CAS
tRCD (Min) ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS
Address
BA
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : CAS Bank delay can be one or more clock period.
36
MB811L323229-12/18
5. DQM0 to DQM3 - Input Mask and Output Disable (@ BL = 4)
CLK
DQM (@ Read)
DQZ2
(2 clocks) High-Z
DQ (@ Read)
Q1
Q2
Q4
End of burst
DQM (@ Write)
DQD
(same clock)
DQ (@ Write)
D1
MASKED
D3
D4
End of burst
6. Precharge Timing (Applied to The Same Bank)
CLK
tRAS (Min)
Command
ACTV
PRE
Note : PRECHARGE means 'PRE' or 'PALL'.
37
MB811L323229-12/18
7. READ Interrupted by Precharge (Example @ CL = 2, BL = 4)
CLK
Command
PRECHARGE
ROH2
(2 clolcks) High-Z
DQ
Q1
Command
PRECHARGE
ROH2
(2 clolcks) High-Z
DQ
Q1
Q2
Command
PRECHARGE
ROH2
(2 clolcks) High-Z
DQ
Q1
Q2
Q3
Command
PRECHARGE No effect (end of burst)
DQ
Q1
Q2
Q3
Q4
Notes : * In case of CL = 2, the ROH2 is 2 clocks. * PRECHARGE means 'PRE' or 'PALL'.
38
MB811L323229-12/18
8. READ Interrupted by Burst Stop (Example @ CL = 2, BL = Full Column)
CLK
Command
BST
BSH2
(2 clocks) High-Z
DQ
Qn - 2
Qn - 1
Qn
Qn + 1
9. WRITE Interrupted by Burst Stop (Example @ BL = 2)
CLK
Command
BST
COMMAND
DQ0
LAST DATA-IN
Masked by BST
39
MB811L323229-12/18
10. WRITE Interrupted by Precharge (Example @ CL = 2)
CLK
Command
WRIT
PRECHARGE tDPL (Min) LAST DATA-IN MASKED by Precharge tRP (Min)
ACTV
DQ
DATA-IN
Note : * The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied. * PRECHARGE means 'PRE' or 'PALL'.
11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)
CLK
OWD
(2 clocks) WRIT
Command
READ
DQM
*1
DQZ
*2 (2 clocks)
*3
DWD
(same clock) D2
DQ
Q1
Masked
D1
*1 : The first DQM makes high-impedance state High-Z between last output and first input data. *2 : The second DQM makes internal output data mask to avoid bus contention. *3 : The third DQM also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
40
MB811L323229-12/18
12. WRITE to READ Timing (Example @ CL = 2, BL = 4)
CLK
tWR (Min) WRIT READ
Command
DQM
(CL - 1) x tCK2
tAC2 (Max)
DQ
D1
D2
D3 Masked by READ Q1 Q2 Q3
Notes : * Read command should be issued after tWR of final data input is satisfied. * The write data after the READ command is masked by the READ command.
13. READ with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to Same Bank)
CLK
tRAS (Min) tRP (Min)
Command
ACTV
READA 2 clocks (same value as BL)
*1
NOP or DESL BL + tRP (Min)
*2
ACTV
DQM
DQ
Q1
Q2
*1 : Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after the READA command is asserted. *2 : The next ACTV command should be issued after BL + tRP (Min) from READA command.
41
MB811L323229-12/18
14. WRITE with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to Same Bank)
tRAS (Min)
CLK
CL + 1
*1
tDAL2 (Min) BL + tRP (Min)
*2
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
DQ
D1
D2
*1 : Precharge at write with Auto-precharge is started after CL - 1 from the end of burst. *2 : The next command should be issued after BL+ tRP (Min) at CL = 2 from WRITA command. Notes: * Even if the final data is masked by DQM, the precharge does not start the clock of final data input. * Once auto precharge command is asserted, no new command within the same bank can be issued. * Auto-precharge command doesn't affect at full column burst operation except Burst READ & Single Write.
15. Auto-Refresh Timing
CLK
Command
REF
*1
NOP
*3
NOP
*3
NOP
*3
REF
NOP
*3
Command *4
tRC (Min)
tRC (Min)
*2
BA
H or L
*2
H or L
BA
*1 : All banks should be precharged prior to the first Auto-refresh command (REF). *2 : Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3 : Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode. *4 : Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the last REF command.
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MB811L323229-12/18
16. Self-Refresh Entry and Exit Timing
CLK
tSI (Min)
tCKSP (Min)
CKE
*6
tRC (Min)
*5
Command
NOP
*1
SELF
*2
H or L
NOP
*3
SELFX
NOP
*4
Command
*1 : The precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF). *2 : SELF command should be issued only after the last read data has been appeared on DQ. *3 : The Self-refresh Exit command (SELFX) is latched after tCKSP (Min). It is recommended to apply NOP command in conjunction with CKE. *4 : Either NOP or DESL command can be used during tRC period. *5 : CKE should be held high within one tRC period after tCKSP . *6 : CKE level should be held less than 0.2 V during self-refresh mode.
17. Mode Register Set Timing
CLK
tRSC (Min)
Command
MRS
NOP or DESL
ACTV
Address
MODE
ROW ADDRESS
Note : The Mode Register Set command (MRS) should only be asserted after all banks have been precharged and DQ is in High-Z.
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MB811L323229-12/18
s ORDERING INFORMATION
Part number MB811L323229-12WFKT MB811L323229-18WFKT Configuration 524,288 word x 32 bit x 2 bank 524,288 word x 32 bit x 2 bank Shipping form wafer wafer Remarks
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MB811L323229-12/18
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0205 (c) FUJITSU LIMITED Printed in Japan

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